HD6432351 datasheet(767/1025 Pages) RENESAS

767 / 1025 page

Appendix A Instruction Set

Rev. 3.00 Sep 15, 2006 page 733 of 988

REJ09B0330-0300

Appendix A Instruction Set

A.1

Instruction List

Operand Notation

General register (destination)*

General register (source)*

General register*

ERn

General register (32-bit register)

MAC

Multiply-and-accumulate register (32-bit register)*

(EAd)

Destination operand

(EAs)

Source operand

EXR

Extended control register

CCR

Condition-code register

N (negative) flag in CCR

Z (zero) flag in CCR

V (overflow) flag in CCR

C (carry) flag in CCR

Program counter

Stack pointer

#IMM

Immediate data

disp

Displacement

Add

–

Subtract

Multiply

Divide

∧

Logical AND

∨

Logical OR

⊕

Logical exclusive OR

→

Transfer from the operand on the left to the operand on the right, or

transition from the state on the left to the state on the right

Logical NOT (logical complement)

( ) < >

Contents of operand

:8/:16/:24/:32

8-, 16-, 24-, or 32-bit length

Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

2. The MAC register cannot be used in the H8S/2350 Group.

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