HD6432351 datasheet(821/1025 Pages) RENESAS

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Appendix A Instruction Set

Rev. 3.00 Sep 15, 2006 page 787 of 988

REJ09B0330-0300

A.5

Bus States during Instruction Execution

Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See

table A.4 for the number of states per cycle.

How to Read the Table:

Instruction

JMP@aa:24

R:W 2nd

Internal operation

1 state

R:W EA

2345

End of instruction

Order of execution

Read effective address (word-size read)

No read or write

Read 2nd word of current instruction

(word-size read)

Legend:

R:B

Byte-size read

R:W

Word-size read

W:B

Byte-size write

W:W

Word-size write

Transfer of the bus is not performed immediately after this cycle

2nd

Address of 2nd word (3rd and 4th bytes)

3rd

Address of 3rd word (5th and 6th bytes)

4th

Address of 4th word (7th and 8th bytes)

5th

Address of 5th word (9th and 10th bytes)

Address of next instruction

Effective address

VEC

Vector address

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