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HD6432351 Datasheet(PDF) 849 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 849 Page - Renesas Technology Corp |
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849 / 1025 page  Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 815 of 988 REJ09B0330-0300 B.2 Functions MRA—DTC Mode Register A H'F800–H'FBFF DTC 7 SM1 Undefined — 6 SM0 Undefined — 5 DM1 Undefined — 4 DM0 Undefined — 3 MD1 Undefined — 0 Sz Undefined — 2 MD0 Undefined — 1 DTS Undefined — Bit Initial value Read/Write : : : 0 1 Source Address Mode — 0 1 0 1 Destination Address Mode — 0 1 DTC Mode 0 1 Normal mode Repeat mode Block transfer mode — 0 1 0 1 DTC Data Transfer Size 0 1 Byte-size transfer DTC Transfer Mode Select 0 1 Word-size transfer Destination side is repeat area or block area Source side is repeat area or block area DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) DAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) SAR is fixed |
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