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HD6432351 Datasheet(PDF) 238 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 238 Page - Renesas Technology Corp |
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238 / 1025 page  Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 204 of 988 REJ09B0330-0300 (2) Repeat Mode Transfer Number Storage Bit ETCRH Initial value R/W : : : : *: Undefined 15 * R/W 14 * R/W 13 * R/W 12 * R/W 11 * R/W 8 * R/W 10 * R/W 9 * R/W 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 0 * R/W 2 * R/W 1 * R/W Transfer Counter Bit ETCRL Initial value R/W : : : : In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. ETCR is not initialized by a reset or in standby mode. |
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