HD6432351 datasheet(245/1025 Pages) RENESAS

245 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 211 of 988

REJ09B0330-0300

Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA

transfer is performed, of the internal interrupt source selected by the channel 1B data transfer

factor setting.

Bit 11

DTA1B

Description

Clearing of selected internal interrupt source at time of DMA transfer is disabled

(Initial value)

Clearing of selected internal interrupt source at time of DMA transfer is enabled

Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA

transfer is performed, of the internal interrupt source selected by the channel 1A data transfer

factor setting.

Bit 10

DTA1A

Description

Clearing of selected internal interrupt source at time of DMA transfer is disabled

(Initial value)

Clearing of selected internal interrupt source at time of DMA transfer is enabled

Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA

transfer is performed, of the internal interrupt source selected by the channel 0B data transfer

factor setting.

Bit 9

DTA0B

Description

Clearing of selected internal interrupt source at time of DMA transfer is disabled

(Initial value)

Clearing of selected internal interrupt source at time of DMA transfer is enabled

Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA

transfer is performed, of the internal interrupt source selected by the channel 0A data transfer

factor setting.

Bit 8

DTA0A

Description

Clearing of selected internal interrupt source at time of DMA transfer is disabled

(Initial value)

Clearing of selected internal interrupt source at time of DMA transfer is enabled

HD6432351 Datasheet(PDF) 245 Page - Renesas Technology Corp