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HD6432351 Datasheet(PDF) 250 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 250 Page - Renesas Technology Corp |
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250 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 216 of 988 REJ09B0330-0300 7.3.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. (1) Normal Mode ETCRA: 0 * R/W 2 * R/W 1 * R/W 3 * R/W 4 * R/W 5 * R/W 6 * R/W 7 * R/W 8 * R/W 9 * R/W 10 * R/W 11 * R/W 12 * R/W 13 * R/W 14 * R/W 15 * R/W Bit ETCR Initial value R/W Transfer Counter : : : : *: Undefined In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used at this time. ETCRB: ETCRB is not used in normal mode. |
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