HD6432351 datasheet(311/1025 Pages) RENESAS

311 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 277 of 988

REJ09B0330-0300

DREQ

DREQ Pin Low Level Activation Timing

Set the DTA bit for the channel for which the

DREQ pin is selected to 1.

Figure 7.32 shows an example of

DREQ pin low level activated single address mode transfer.

DREQ

Bus release

DMA single

Address bus

DMA control

Channel

[2]

DACK

Transfer source/

destination

Idle

Single

[1]

[3]

[5]

[4]

[6]

[7]

Acceptance resumes

Bus release

DMA single

Bus

release

Transfer source/

destination

Request

Minimum of

2 cycles

Minimum of

2 cycles

Request clear

period

Request clear

period

[1]

[2] [5]

[3] [6]

[4] [7]

Acceptance after transfer enabling; the

DREQ pin low level is sampled on the rising

edge of

φ, and the request is held.

The request is cleared at the next bus break, and activation is started in the DMAC.

The DMAC cycle is started.

Acceptance is resumed after the single cycle is completed.

(As in [1], the

DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 7.32 Example of

DREQ

DREQ Pin Low Level Activated Single Address Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the

DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the

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