| Electronic Components Datasheet Search |
|
HD64F2149YV Datasheet(PDF) 357 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD64F2149YV Datasheet(HTML) 357 Page - Renesas Technology Corp |
|
357 / 1075 page ![]() Section 11 16-Bit Free-Running Timer Rev. 3.00 Jan 18, 2006 page 329 of 1044 REJ09B0280-0300 11.3.2 Output Compare Output Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A. N + 1 N N + 1 N N OCRA φ Compare-match A signal FRC OLVLA Output compare A output pin FTOA Clear* Note: * Vertical arrows ( ) indicate instructions executed by software. N Figure 11.5 Timing of Output Compare A Output |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |