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HD64F2149YV Datasheet(PDF) 510 Page - Renesas Technology Corp

Part # HD64F2149YV
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV Datasheet(HTML) 510 Page - Renesas Technology Corp

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Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 3.00 Jan 18, 2006 page 482 of 1044
REJ09B0280-0300
In serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with serial clock input or output.
2. The received data is stored in RSR in LSB-to-MSB order.
After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be
transferred from RSR to RDR.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a
receive error is detected in the error check, the operation is as shown in table 15.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
3. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
Figure 15.19 shows an example of SCI operation in reception.
Bit 7
Serial
data
Serial
clock
1 frame
RDRF
ORER
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RXI interrupt request
generated
RDR data read and
RDRF flag cleared to 0
in RXI interrupt handling
routine
RXI interrupt request
generated
ERI interrupt request
generated by overrun
error
Figure 15.19 Example of SCI Operation in Reception
Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.20
shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations.



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