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HD64F2149YV Datasheet(PDF) 523 Page - Renesas Technology Corp |
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HD64F2149YV Datasheet(HTML) 523 Page - Renesas Technology Corp |
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523 / 1075 page  Section 16 I 2C Bus Interface Rev. 3.00 Jan 18, 2006 page 495 of 1044 REJ09B0280-0300 φ PS Noise canceler Noise canceler Clock control Formatless dedicated clock (channel 0 only) Bus state decision circuit Arbitration decision circuit Output data control circuit Address comparator SAR, SARX Interrupt generator ICDRS ICDRR ICDRT ICSR ICMR ICCR Interrupt request SCL SDA Legend: ICCR: ICMR: ICSR: ICDR: SAR: SARX: PS: I2C bus control register I2C bus mode register I2C bus status register I2C bus data register Slave address register Slave address register X Prescaler Figure 16.1 Block Diagram of I 2C Bus Interface |
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