HD64F2149YV datasheet(539/1075 Pages) RENESAS

539 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 511 of 1044

REJ09B0280-0300

When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously

without CPU intervention.

Bit 1

IRIC

Description

Waiting for transfer, or transfer in progress

(Initial value)

[Clearing conditions]

When 0 is written in IRIC after reading IRIC = 1

When ICDR is written or read by the DTC

(When the TDRE or RDRF flag is cleared to 0)

(This is not always a clearing condition; see the description of DTC operation for details)

Interrupt requested

[Setting conditions]

•

2C bus format master mode

When a start condition is detected in the bus line state after a start condition is issued

(when the TDRE flag is set to 1 because of first frame transmission)

When a wait is inserted between the data and acknowledge bit when WAIT = 1

At the end of data transfer

(When a wait is not inserted(WAIT=0), at the rise of the 9th transmit/receive clock pulse,

or, when a wait is inserted(WAIT=1), at the fall of the 8th transmit/receive clock pulse)

When a slave address is received after bus arbitration is lost

(when the AL flag is set to 1)

When 1 is received as the acknowledge bit when the ACKE bit is 1

(when the ACKB bit is set to 1)

•

2C bus format slave mode

When the slave address (SVA, SVAX) matches

(when the AAS and AASX flags are set to 1)

and at the end of data transfer up to the subsequent retransmission start condition or

stop condition detection

(when the TDRE or RDRF flag is set to 1)

When the general call address is detected

(when FS = 0 and the ADZ flag is set to 1)

and at the end of data transfer up to the subsequent retransmission start condition or

stop condition detection

(when the TDRE or RDRF flag is set to 1)

When 1 is received as the acknowledge bit when the ACKE bit is 1

(when the ACKB bit is set to 1)

When a stop condition is detected

(when the STOP or ESTP flag is set to 1)

•

Synchronous serial format, and formatless mode

At the end of data transfer

(when the TDRE or RDRF flag is set to 1)

When a start condition is detected with serial format selected

When the SW bit is set to 1 in DDCSWR

When any other condition arises in which the TDRE or RDRF flag is set to 1.

HD64F2149YV Datasheet(PDF) 539 Page - Renesas Technology Corp

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