HD64F2149YV datasheet(550/1075 Pages) RENESAS

550 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 522 of 1044

REJ09B0280-0300

Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal

state of IIC0 and IIC1.

These bits can only be written to; if read they will always return a value of 1.

When a write operation is performed on these bits, a clear signal is generated for the internal latch

circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized.

The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be

written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction

such as BCLR.

When clearing is required again, all the bits must be written to in accordance with the setting.

Bit 3

Bit 2

Bit 1

Bit 0

CLR3

CLR2

CLR1

CLR0

Description

——

Setting prohibited

IIC0 internal latch cleared

IIC1 internal latch cleared

IIC0 and IIC1 internal latches cleared

——

—

Invalid setting

16.2.9

Module Stop Control Register (MSTPCR)

MSTP15

R/W

Bit

Initial value

Read/Write

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRH

MSTPCRL

MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop

mode control.

When the MSTP4 or MSTP3 bit is set to 1, operation of the corresponding IIC channel is halted at

the end of the bus cycle, and a transition is made to module stop mode. For details, see section

24.5, Module Stop Mode.

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