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HD64F2149YV Datasheet(PDF) 571 Page - Renesas Technology Corp |
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HD64F2149YV Datasheet(HTML) 571 Page - Renesas Technology Corp |
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571 / 1075 page  Section 16 I 2C Bus Interface Rev. 3.00 Jan 18, 2006 page 543 of 1044 REJ09B0280-0300 16.3.11 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in the DDCSWR register or clearing ICE bit. For details the setting of bits CLR3 to CLR0, see section 16.2.8, DDC Switch Register (DDCSWR). Scope of Initialization: The initialization executed by this function covers the following items: • TDRE and RDRF internal flags • Transmit/receive sequencer and internal operating clock counter • Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) The following items are not initialized: • Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR) • Internal latches used to retain register read information for setting/clearing flags in the ICMR, ICCR, ICSR, and DDCSWR registers • The value of the ICMR register bit counter (BC2 to BC0) • Generated interrupt sources (interrupt sources transferred to the interrupt controller) |
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