HD64F2149YV datasheet(600/1075 Pages) RENESAS

Part #	HD64F2149YV

Description	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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600 / 1075 page

Section 17 Keyboard Buffer Controller

Rev. 3.00 Jan 18, 2006 page 572 of 1044

REJ09B0280-0300

KCLK

(pin state)

KCLK

(output)

KCLK

(input)

Start bit

Parity bit Stop bit

I/O inhibit

Receive

completed

notification

[1]

[2] [3]

[4] [5]

[6]

[7]

[8]

Figure 17.6 Transmit Timing

17.3.3

Receive Abort

The H8S/2169 or H8S/2149 device (system side) can forcibly abort transmission from the device

connected to it (keyboard side) in the event of a protocol error, etc. In this case, the system holds

the clock low. During reception, the keyboard also outputs a clock for synchronization, and the

clock is monitored when the keyboard output clock is high. If the clock is low at this time, the

keyboard judges that there is an abort request from the system, and data transmission from the

keyboard is aborted. Thus the system can abort reception by holding the clock low for a certain

period. A sample receive abort processing flowchart is shown in figure 17.7, and the receive abort

timing in figure 17.8.

HD64F2149YV Datasheet(PDF) 600 Page - Renesas Technology Corp