HD64F2149YV datasheet(713/1075 Pages) RENESAS

713 / 1075 page

Section 21 RAM

Rev. 3.00 Jan 18, 2006 page 685 of 1044

REJ09B0280-0300

21.3

Operation

21.3.1

Expanded Mode (Modes 1 to 3 (EXPE = 1))

When the RAME bit is set to 1, accesses to H8S/2169 or H8S/2149 addresses H'(FF)E880 to

H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the on-chip RAM. When the RAME

bit is cleared to 0, accesses to addresses H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to

H'(FF)FF7F, are directed to the external address space.

Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to

and read in byte or word units. Each type of access is performed in one state.

Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start

at an even address.

21.3.2

Single-Chip Mode (Modes 2 and 3 (EXPE = 0))

When the RAME bit is set to 1, accesses to H8S/2169 or H8S/2149 addresses H'(FF)E880 to

H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the on-chip RAM. When the RAME

bit is cleared to 0, the on-chip RAM is not accessed. Undefined values are always read from these

bits, and writing is invalid.

Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to

and read in byte or word units. Each type of access is performed in one state.

Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start

at an even address.

HD64F2149YV Datasheet(PDF) 713 Page - Renesas Technology Corp