HD64F2149YV datasheet(733/1075 Pages) RENESAS

733 / 1075 page

Section 22 ROM

Rev. 3.00 Jan 18, 2006 page 705 of 1044

REJ09B0280-0300

n = N?

Yes

Set pins to boot mode and execute reset-start

n = 1

n + 1

→ n

Host transfers data (H'00) continuously at prescribed

bit rate

The chip measures low period of H'00 data transmitted

by host

After bit rate adjustment, transmits one H'00 data byte

to host to indicate end of adjustment

Host confirms normal reception of bit rate adjustment

end indication (H'00), and transmits one H'55 data byte

After receiving H'55, trransmit one H'AA data byte

to host

Host transmits number of user program bytes (N),

upper byte followed by lower byte

The chip transmits received number of bytes to host as

verify data (echo-back)

Host transmits programming control program

sequentially in byte units

The chip transmits received programming control

program to host as verify data (echo-back)

Transfer received programming control program

to on-chip RAM

End of transmission

Transmit one H'AA byte to host

Check flash memory data, and if data has already

been written, erase all blocks

Confirm that all flash memory data has been erased

Check ID code at beginning of user program transfer

area

Execute programming control program transferred

to on-chip RAM

Start

The chip calculates bit rate and sets value in bit rate

Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and

the erase operation and subsequent operations are halted.

ID code match?

Transfer 1-byte of H'FF

data as an ID code

error indicator and halt

other operations

Figure 22.8 Boot Mode Execution Procedure

HD64F2149YV Datasheet(PDF) 733 Page - Renesas Technology Corp

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