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H8SX/1663M Datasheet(PDF) 414 Page - Renesas Technology Corp |
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H8SX/1663M Datasheet(HTML) 414 Page - Renesas Technology Corp |
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414 / 1504 page ![]() Section 10 DMA Controller (DMAC) Rev. 2.00 Sep. 24, 2008 Page 382 of 1468 REJ09B0412-0200 10.3.3 DMA Offset Register (DOFR) DOFR is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. Although different values are specified for individual channels, the same values must be specified for the source and destination sides of a single channel. 31 0 R/W 30 0 R/W 29 0 R/W 28 0 R/W 27 0 R/W 24 0 R/W 26 0 R/W 25 0 R/W Bit Bit Name Initial Value R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 16 0 R/W 18 0 R/W 17 0 R/W Bit Bit Name Initial Value R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 8 0 R/W 10 0 R/W 9 0 R/W Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 0 0 R/W 2 0 R/W 1 0 R/W Bit Bit Name Initial Value R/W |
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