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M32C/86T Datasheet(PDF) 248 Page - Renesas Technology Corp |
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M32C/86T Datasheet(HTML) 248 Page - Renesas Technology Corp |
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248 / 505 page  Page 225 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 17. Serial I/O (Special Function) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Trigger Signal from the CTSi Pin External Clock from the CLKi Pin Transfer Clock TxDi A Transfer Clock i=0 to 4 A, B : See Table 17.29. TxDi B 12345678 12345678 1234567 8 The SCLKSTPB bit in the UiC1 register stops the clock To generate the internal clock synchronized with the external clock, set the SU1HIM bit in the UiSMR2 register (i=0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 17.29. Then apply ________ a trigger signal to the CTSi pin. Either the same clock cycle as the external clock or external clock divided by two can be selected as the transfer clock. The SCLKSTPB bit in the UiC1 register controls the transfer clock. Set the SCLKSTPB bit accordingly, to start or stop the transfer clock during an external clock operation. Figure 17.27 shows an example of the clock-divided synchronous function. Table 17.29 Clock-Divided Synchronous Function Select SCLKDIV Bit in SU1HIM Bit in Clock-Divided Synchronous Function Example of Waveform UiSMR Register UiSMR2 Register 0 0 Not synchronized - 0 1 Same division as the external clock A in Figure 17.27 1 0 or 1 Same division as the external clock B in Figure 17.27 divided by 2 i=0 to 4 Figure 17.27 Clock-Divided Synchronous Function |
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