M16CSLASH62 datasheet(373/621 Pages) RENESAS

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UART

Mitsubishi microcomputers

M16C / 62 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

358

In transmitting data in UART mode, choose functions from those listed in Table 2.5.4. Operations of the

circled items are described below. Figure 2.5.8 shows the operation timing, and Figures 2.5.9 and 2.5.10

show the set-up procedures.

2.5.2 Operation of Serial I/O (transmission in UART mode)

Item

Set-up

Transfer clock

source

(Note 2)

Internal clock (f1 / f8 / f32)

External clock (CLKi pin)

CTS function

CTS function enabled

CTS function disabled

Transmission

interrupt factor

Transmission buffer empty

Transmission complete

CTS / RTS

separation function

(Note 1)

Pin shared by CTS and RTS

CTS and RTS separate

Sleep mode

(Note 2)

Sleep mode off

Sleep mode selected

Item

Set-up

Data logic select

function

(Note 3)

No reverse

Reverse

TXD, RXD I/O

polarity reverse bit

(Note 3)

No reverse

Reverse

Bus collision

detection function

(Note 3)

Not selected

Selected

Table 2.5.4. Choosed functions

_______________

Note 1: UART0 only. (UART1 CTS/RTS function cannot be used when this function is selected.)

Note 2: UART0, UART1 only.

Note 3: UART2 only.

(1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit

buffer register readies the data transmissible status.

________

(2) When input to the CTSi pin goes to “L”, transmission starts (the CTSi pin needs to be con-

trolled on the reception side).

(3) Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi

transmit register. At this time, the first bit (the start bit) of the transmission data is transmitted

from the TxDi pin. Then, data is transmitted, bit by bit, in sequence: LSB, ····, MSB, parity bit,

and stop bit(s).

(4) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which

indicates that transmission is completed. At this time, the UARTi transmit interrupt request bit

goes to “1”. The transfer clock stops at “H” level.

(5) If the transmission condition of the next data is ready when transmission is completed, a start

bit is generated following to stop bit(s), and the next data is transmitted.

Operation

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