M16CSLASH62 datasheet(218/621 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 3V)

203

td(BCLK-AD)

Address output delay time

td(BCLK-CS)

Chip select output delay time

th(BCLK-AD)

Address output hold time (BCLK standard)

th(BCLK-CS)

Chip select output hold time (BCLK standard)

td(BCLK-ALE)

ALE signal output delay time

th(BCLK-ALE)

ALE signal output hold time

—

td(BCLK-RD)

RD signal output delay time

th(BCLK-RD)

RD signal output hold time

th(RD-AD)

Address output hold time (RD standard)

td(BCLK-WR)

WR signal output delay time

th(BCLK-WR)

WR signal output hold time

th(WR-AD)

Address output hold time (WR standard)

td(BCLK-DB)

Data output delay time (BCLK standard)

th(BCLK-DB)

Data output hold time (BCLK standard)

td(DB-WR)

Data output delay time (WR standard)

(Note1)

th(WR-DB)

Data output hold time (WR standard)(Note2)

Note 1: Calculated according to the BCLK frequency as follows:

td(DB – WR) =

f(BCLK) X 2

– 80

[ns]

Symbol

Standard

Measuring condition

Max.

Min.

Parameter

Unit

Note 2: This is standard value shows the timing when the output is off,

and doesn't show hold time of data bus.

Hold time of data bus is different by capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

t = –CR X ln (1 – VOL / VCC)

by a circuit of the right figure.

For example, when VOL = 0.2VCC, C = 30pF, R = 1k

Ω, hold time

of output “L” level is

t = – 30pF X 1k

Ω X ln (1 – 0.2VCC / VCC)

= 6.7ns.

DBi

Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, CM15 = “1” unless

otherwise specified)

VCC = 3V

Figure 1.26.1

Table 1.26.38. Memory expansion and microprocessor modes (with no wait)

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