M38K02FDFP datasheet(143/328 Pages) RENESAS

143 / 328 page

2.2 Interrupt

Rev.2.00

Oct 05, 2006

page 14 of 111

38K0 Group

REJ09B0337-0200

APPLICATION

(2)

Timing after acceptance of interrupt request

The interrupt processing routine begins with the machine cycle following the completion of the

instruction that is currently being executed.

Figure 2.2.9 shows the time up to execution of interrupt processing routine and Figure 2.2.10 shows

the timing chart after acceptance of interrupt request.

Fig. 2.2.10 Timing chart after acceptance of interrupt request

Fig. 2.2.9 Time up to execution of interrupt processing routine

Interrupt request generated

Main routine

Interrupt processing routine

7 to 23 cycles

(When f(XIN) = 6 MHz; system clock 8 MHz

/through mode (8 MHz), 0.875

µs to 2.875 µs)

2 cycles

5 cycles

Start of interrupt processing

0 to 16 cycles

Waiting time for

post-processing of

pipeline

Stack push and

Vector fetch

✽

✽ When executing DIV instruction

PCH

PCL

S, SPS

S-2, SPS

S-1, SPS

AL, AH

: CPU operation code fetch cycle

(This is an internal signal that cannot be observed from the external unit.)

: Vector address of each interrupt

: Jump destination address of each interrupt

: “0016” or “0116”

SYNC

BL, BH

AL, AH

SPS

Data bus

Not used

Address bus

SYNC

Waiting time for pipeline

post-processing

Push onto stack

Vector fetch

Interrupt operation starts

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