M38K02FDFP datasheet(216/328 Pages) RENESAS

Part #	M38K02FDFP

Description	RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES

PDF	328 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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216 / 328 page

2.10 Frequency synthesizer (PLL)

Rev.2.00

Oct 05, 2006

page 87 of 111

38K0 Group

REJ09B0337-0200

APPLICATION

q Procedure for stop and return of PLL circuit when stop mode

Figure 2.10.7 shows the stop procedure of PLL circuit, and figure 2.10.8 shows the return procedure

of PLL circuit.

Fig. 2.10.7 Related registers setting when stop mode

q X: This bit is not used here.

Set it to “0” or “1” arbitrarily.

•Select main clock f(XIN) as a system clock

•Disable PLL operation (bit7)

(fVCO is fixed to “L”.)

•Select PLL circuit output clock fVCO as a USB clock

and does not change this setting

CPUM (address: 3B16)

← 11001X002

PLLCON (address: 0FF816)

← 0XXXX0002

USBCON (address: 1016)

← X1XXXXXX2

PLL circuit operation enabled

(Supply PLL circuit output clock fVCO as USB clock)

STP instruction (stop mode)

•Stop mode

Note: The above setting example assumes the operation when the external oscillating clock is 6 MHZ and

the internal system clock is fSYN.

M38K02FDFP Datasheet(PDF) 216 Page - Renesas Technology Corp