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AT52SC1284J-70CI Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT52SC1284J-70CI Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 52 page  7 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 6.9 Reset A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read mode. 6.10 Erase Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical “1”. The entire memory can be erased by using the Chip Erase command or individual planes can be erased by using the Plane Erase command or individual sectors can be erased by using the Sector Erase command. 6.10.1 Chip Erase Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset during chip erase will stop the erase, but the data will be of an unknown state. 6.10.2 Plane Erase As an alternative to a full Chip Erase, the device is organized into thirty-two planes (PA0 - PA31). The Plane Erase command is a two-bus cycle operation which can be used to individu- ally erase any one of the thirty (PA1 - PA30) planes. The plane whose address is valid at the second rising edge of WE will be erased. The Plane Erase command does not alter the data in the protected sectors. 6.10.3 Sector Erase The device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose address is valid at the second rising edge of WE will be erased provided the given sector has not been protected. 6.11 Word Programming The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a two-bus cycle operation. The programming address and data are latched in the second cycle. The device will automatically generate the required internal programming pulses. Please note that a “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. 6.12 Flexible Sector Protection The AT52SC1283J/1284J offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes fre- quently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently pro- grammed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled. |
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