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AT52SC1284J-70CI Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT52SC1284J-70CI Datasheet(HTML) 5 Page - ATMEL Corporation |
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5 / 52 page  5 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] the device. The access time is measured from stable address, falling edge of AVD or falling edge of CE, whichever occurs last. During the AVD pulsed read, the CLK signal may be static high or static low. For standard asynchronous reads, the AVD and CLK signal should be tied to GND. The asynchronous read diagrams are shown on page 30. 6.4 Page Read The page read operation of the device is controlled by CE, OE, and AVD inputs. The CLK input is ignored during a page read operation and should be tied to GND. The page size is four words. During a page read, the AVD signal can transition low and then transition high, transition low and remain low, or can be tied to GND. If a high to low transition on the AVD signal occurs, as shown in Page Read Cycle Waveform 1, the page address is latched by the low-to-high transition of the AVD signal. However, if the AVD signal remains low after the high-to-low transition or if the AVD signal is tied to GND, as shown in Page Read Cycle Waveform 2, then the page address (A22 - A2) cannot change during a page read operation. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads within the page being output at a speed of 20 ns. If the AVD and the CLK pins are both tied to GND, the device will behave like a standard asynchronous Flash memory. The page read diagrams are shown on page 23. 6.5 Synchronous Reads Synchronous reads are used to achieve a faster data rate that is possible in the asynchro- nous/page read mode. The device can be configured for continuous or fixed-length burst access. The burst read operation of the device is controlled by CE, OE, CLK and AVD inputs. The initial read location is determined as for the AVD pulsed asynchronous read operation; it can be any memory location in the device. In the burst access, the address is latched on the rising edge of the first clock pulse when AVD is low or the rising edge of the AVD signal, whichever occurs first. The CLK input signal controls the flow of data from the device for a burst operation. After the clock latency cycles, the data at the next burst address location is read for each follow- ing clock cycle. Figure 6-1. Word Boundary 6.6 Continuous Burst Read During a continuous burst read, any number of addresses can be read from the memory. When operating in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence crosses the first 16-word boundary in the memory (see Figure 6-1). If the starting address is D0 - D12, there is no delay. If the starting address is D13 - D15, an output delay equal to the initial clock latency is incurred. The delay 16-word Boundary Word D0 - D3 Word D4 - D7 Word D8 - D11 Word D12 - D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 |
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