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PIC18F2420-E/P Datasheet(PDF) 165 Page - Microchip Technology

Part # PIC18F2420-E/P
Description  28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PDF  412 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F2420-E/P Datasheet(HTML) 165 Page - Microchip Technology

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© 2008 Microchip Technology Inc.
DS39631E-page 163
PIC18F2420/2520/4420/4520
REGISTER 17-2:
SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV(1)
SSPEN(2)
CKP
SSPM3(3)
SSPM2(3)
SSPM1(3)
SSPM0(3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL:
Write Collision Detect bit
1
= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0
= No collision
bit 6
SSPOV:
Receive Overflow Indicator bit(1)
SPI Slave mode:
1
= A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0
= No overflow
bit 5
SSPEN:
Master Synchronous Serial Port Enable bit(2)
1
= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0
= Disables serial port and configures these pins as I/O port pins
bit 4
CKP:
Clock Polarity Select bit
1
= Idle state for clock is a high level
0
= Idle state for clock is a low level
bit 3-0
SSPM<3:0>:
Master Synchronous Serial Port Mode Select bits(3)
0101
= SPI Slave mode, clock = SCK pin; SS pin control disabled; SS can be used as I/O pin
0100
= SPI Slave mode, clock = SCK pin; SS pin control enabled
0011
= SPI Master mode, clock = TMR2 output/2
0010
= SPI Master mode, clock = FOSC/64
0001
= SPI Master mode, clock = FOSC/16
0000
= SPI Master mode, clock = FOSC/4
Note 1:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2:
When enabled, these pins must be properly configured as input or output.
3:
Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.



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