PIC18F44J10-ISLASHMLQTP datasheet(225/368 Pages) MICROCHIP

225 / 368 page

DS39682E-page 223

PIC18F45J10 FAMILY

18.7

A/D Converter Calibration

The A/D converter in the PIC18F45J10 family of

devices includes a self-calibration feature which com-

pensates for any offset generated within the module.

The calibration process is automated and is initiated by

setting the ADCAL bit (ADCON0<7>). The next time

the GO/DONE bit is set, the module will perform a

“dummy” conversion (that is, with reading none of the

input channels) and store the resulting value internally

to compensate for offset. Thus, subsequent offsets will

be compensated.

The calibration process assumes that the device is in a

relatively steady-state operating condition. If A/D

calibration is used, it should be performed after each

device Reset or if there are other major changes in

operating conditions.

18.8

Operation in Power-Managed

Modes

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ACQT<2:0> and

ADCS<2:0> bits in ADCON2 should be updated in

accordance with the power-managed mode clock that

will be used. After the power-managed mode is entered

(either of the power-managed Run modes), an A/D

acquisition or conversion may be started. Once an

acquisition or conversion is started, the device should

continue to be clocked by the same power-managed

mode clock source until the conversion has been com-

pleted. If desired, the device may be placed into the

corresponding power-managed Idle mode during the

conversion.

If the power-managed mode clock frequency is less

than 1 MHz, the A/D RC clock source should be

selected.

Operation in the Sleep mode requires the A/D RC clock

to be selected. If bits, ACQT<2:0>, are set to ‘000’ and

a conversion is started, the conversion will be delayed

one instruction cycle to allow execution of the SLEEP

instruction and entry to Sleep mode. The IDLEN and

SCS bits in the OSCCON register must have already

been cleared prior to starting the conversion.

TABLE 18-2:

REGISTERS ASSOCIATED WITH A/D OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSP1IF

CCP1IF

TMR2IF

TMR1IF

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSP1IE

CCP1IE

TMR2IE

TMR1IE

IPR1

PSPIP(1)

ADIP

RCIP

TXIP

SSP1IP

CCP1IP

TMR2IP

TMR1IP

PIR2

OSCFIF

CMIF

—

BCL1IF

—

CCP2IF

PIE2

OSCFIE

CMIE

—

BCL1IE

—

CCP2IE

IPR2

OSCFIP

CMIP

—

BCL1IP

—

CCP2IP

ADRESH

A/D Result Register High Byte

ADRESL

A/D Result Register Low Byte

ADCON0

ADCAL

—

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

ADCON1

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

ADCON2

ADFM

—

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

PORTA

—

—RA5

—

RA3

RA2

RA1

RA0

TRISA

—

TRISA5

—

TRISA3

TRISA2

TRISA1

TRISA0

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

TRISB

PORTB Data Direction Control Register

LATB

PORTB Data Latch Register (Read and Write to Data Latch)

PORTE(1)

—

—RE2

RE1

RE0

TRISE(1)

IBF

OBF

IBOV

PSPMODE

—

TRISE2

TRISE1

TRISE0

LATE(1)

—

PORTE Data Latch Register

(Read and Write to Data Latch)

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.

Note 1:

These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.

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