PIC18F44J10-ISLASHSOSQTP datasheet(223/368 Pages) MICROCHIP

223 / 368 page

DS39682E-page 221

PIC18F45J10 FAMILY

18.2

Selecting and Configuring

Automatic Acquisition Time

The ADCON2 register allows the user to select an

acquisition time that occurs each time the GO/DONE

bit is set.

When the GO/DONE bit is set, sampling is stopped and

a conversion begins. The user is responsible for ensur-

ing the required acquisition time has passed between

selecting the desired input channel and setting the

GO/DONE bit. This occurs when the ACQT<2:0> bits

(ADCON2<5:3>) remain in their Reset state (‘000’) and

is compatible with devices that do not offer

programmable acquisition times.

If desired, the ACQT bits can be set to select a pro-

grammable acquisition time for the A/D module. When

the GO/DONE bit is set, the A/D module continues to

sample the input for the selected acquisition time, then

automatically begins a conversion. Since the acquisi-

tion time is programmed, there may be no need to wait

for an acquisition time between selecting a channel and

setting the GO/DONE bit.

In either case, when the conversion is completed, the

GO/DONE bit is cleared, the ADIF flag is set and the

A/D begins sampling the currently selected channel

again. If an acquisition time is programmed, there is

nothing to indicate if the acquisition time has ended or

if the conversion has begun.

18.3

Selecting the A/D Conversion

Clock

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 11 TAD per 10-bit conversion.

The source of the A/D conversion clock is software

selectable.

There are seven possible options for TAD:

•2 TOSC

•4 TOSC

•8 TOSC

•16 TOSC

•32 TOSC

•64 TOSC

• Internal RC Oscillator

For correct A/D conversions, the A/D conversion clock

(TAD) must be as short as possible but greater than the

minimum TAD (see parameter 130 in Table 24-25 for

more information).

Table 18-1 shows the resultant TAD times derived from

the device operating frequencies and the A/D clock

source selected.

TABLE 18-1:

TAD vs. DEVICE OPERATING

FREQUENCIES

18.4

Configuring Analog Port Pins

The ADCON1, TRISA, TRISF and TRISH registers

control the operation of the A/D port pins. The port pins

needed as analog inputs must have their correspond-

ing TRIS bits set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) will be

converted.

The A/D operation is independent of the state of the

CHS<3:0> bits and the TRIS bits.

AD Clock Source (TAD)Maximum

Device

Frequency

Operation

ADCS<2:0>

2 TOSC

000

2.86 MHz

4 TOSC

100

5.71 MHz

8 TOSC

001

11.43 MHz

16 TOSC

101

22.86 MHz

32 TOSC

010

40.0 MHz

64 TOSC

110

40.0 MHz

RC(2)

x11

1.00 MHz(1)

Note 1:

The RC source has a typical TAD time of

μs.

For device frequencies above 1 MHz, the

device must be in Sleep mode for the entire

conversion or the A/D accuracy may be out

of specification.

Note 1:

When reading the PORT register, all pins

configured as analog input channels will

read as cleared (a low level). Pins config-

ured as digital inputs will convert an

analog input. Analog levels on a digitally

configured input will

accurately

converted.

Analog levels on any pin defined as a

digital input may cause the digital input

buffer to consume current out of the

device’s specification limits.

PIC18F44J10-I/SOSQTP Datasheet(PDF) 223 Page - Microchip Technology

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