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AT90SCR100 Datasheet(PDF) 257 Page - ATMEL Corporation

Part # AT90SCR100
Description  8-bit Microcontroller for Smart Card Readers
PDF  433 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90SCR100 Datasheet(HTML) 257 Page - ATMEL Corporation

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257
TPR0327AY–SMS–30Jan09
AT90SCR100
19. USART in SPI Mode
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be
set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the follow-
ing features:
19.1
Features
• Full Duplex, Three-wire Synchronous Data Transfer
• Master Operation
• Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
• LSB First or MSB First Data Transfer (Configurable Data Order)
• Queued Operation (Double Buffered)
• High Resolution Baud Rate Generator
• High Speed Operation (fXCKmax = fCK/2)
• Flexible Interrupt Generation
19.2
Overview
Setting both UMSEL01:0 bits to one enables the USART in MSPIM logic. In this mode of opera-
tion the SPI master control logic takes direct control over the USART resources. These
resources include the transmitter and receiver shift register and buffers, and the baud rate gen-
erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX
control logic is disabled. The USART RX and TX control logic is replaced by a common SPI
transfer control logic. However, the pin control logic and interrupt generation logic is identical in
both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the
control registers changes when using MSPIM.
19.3
Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For
USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-
ported. The Data Direction Register for the XCK0 pin (DDR_XCK0) must therefore be set to one
(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCK0 should
be set up before the USART in MSPIM is enabled (i.e. TXEN0 and RXEN0 bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-
ter mode. The baud rate or UBRR0 setting can therefore be calculated using the same
equations, see Table 19-1:



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