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AT90SCR100 Datasheet(PDF) 303 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 303 Page - ATMEL Corporation |
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303 / 433 page  303 TPR0327AY–SMS–30Jan09 AT90SCR100 Figure 22-9. Overview of the TWI Module 22.5.1 SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. Note that SDA and SCL pads supports internal pull-ups. The internal pull-ups can in some systems eliminate the need for external ones. 22.5.2 Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is con- trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to the following equation: • TWBR = Value of the TWI Bit Rate Register. Address Register (TWAR) Address Match Unit Address Comparator Control Unit Control Register (TWCR) Status Register (TWSR) State Machine and Status control SCL Slew-rate Control Spike Filter SDA Slew-rate Control Spike Filter Bit Rate Generator Bit Rate Register (TWBR) Prescaler Bus Interface Unit START / STOP Control Arbitration detection Ack Spike Suppression Address/Data Shift Register (TWDR) SCL frequency CPU Clock frequency 16 2(TWBR) 4 TW PS ⋅ + ----------------------------------------------------------- = |
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