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AT90SCR100 Datasheet(PDF) 431 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 431 Page - ATMEL Corporation |
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431 / 433 page ![]() 431 TPR0327AY–SMS–30Jan09 AT90SCR100 24.2 RNG Definition ...............................................................................................335 24.3 Random Number Generator Registers ..........................................................336 25 AES 128/256 Engine ............................................................................. 339 25.1 Features ........................................................................................................339 25.2 Overview ........................................................................................................339 25.3 AES Registers description .............................................................................341 25.4 Example. Code Sample .................................................................................343 26 JTAG Interface and On-chip Debug System ..................................... 347 26.1 Features ........................................................................................................347 26.2 Overview ........................................................................................................347 26.3 TAP – Test Access Port ................................................................................347 26.4 TAP Controller ...............................................................................................349 26.5 Using the Boundary-scan Chain ....................................................................350 26.6 Using the On-chip Debug System .................................................................350 26.7 On-chip Debug Specific JTAG Instructions ...................................................351 26.8 On-chip Debug Related Register in I/O Memory ...........................................352 26.9 Using the JTAG Programming Capabilities ...................................................352 26.10 Bibliography ...................................................................................................352 27 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 353 27.1 Features ........................................................................................................353 27.2 System Overview ...........................................................................................353 27.3 Data Registers ...............................................................................................353 27.4 Boundary-scan Specific JTAG Instructions ...................................................355 27.5 Boundary-scan Related Register in I/O Memory ...........................................356 27.6 Boundary-scan Chain ....................................................................................357 27.7 AT90SCR100 Boundary-scan Order .............................................................360 27.8 Boundary-scan Description Language Files ..................................................362 28 Boot Loader Support - Read-While-Write Self-Programming .......... 363 28.1 Boot Loader Features ....................................................................................363 28.2 Application and Boot Loader Flash Sections .................................................363 28.3 Read-While-Write and No Read-While-Write Flash Sections ........................364 28.4 Boot Loader Lock Bits ...................................................................................366 28.5 Entering the Boot Loader Program ................................................................367 28.6 Addressing the Flash During Self-Programming ...........................................369 28.7 Self-Programming the Flash ..........................................................................370 |
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