ATmega16 datasheet(278/357 Pages) ATMEL

278 / 357 page

278

2466S–AVR–05/09

ATmega16(L)

SPI Serial

Programming

Characteristics

For characteristics of the SPI module, see “SPI Timing Characteristics” on page 295.

Figure 138. SPI Serial Programming Waveforms

Programming via

the JTAG Interface

Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,

TMS, TDI and TDO. Control of the reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is

default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared.

Alternatively, if the JTD bit is set, the External Reset can be forced low. Then, the JTD bit will be

cleared after two chip clocks, and the JTAG pins are available for programming. This provides a

means of using the JTAG pins as normal port pins in running mode while still allowing In-System

Programming via the JTAG interface. Note that this technique can not be used when using the

JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedi-

cated for this purpose.

As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.

Programming Specific

JTAG Instructions

The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions

useful for Programming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

describes which Data Register is selected as path between TDI and TDO for each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be

used as an idle state between JTAG sequences. The state machine sequence for changing the

instruction word is shown in Figure 139.

MSB

LSB

SERIAL CLOCK INPUT

(SCK)

SERIAL DATA INPUT

(MOSI)

(MISO)

SAMPLE

SERIAL DATA OUTPUT

ATmega16 Datasheet(PDF) 278 Page - ATMEL Corporation