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ATmega16 Datasheet(PDF) 286 Page - ATMEL Corporation |
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ATmega16 Datasheet(HTML) 286 Page - ATMEL Corporation |
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286 / 357 page  286 2466S–AVR–05/09 ATmega16(L) Figure 142. State Machine Sequence for Changing/Reading the Data Word Virtual Flash Page Load Register The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically trans- ferred to the Flash page buffer byte by byte. Shift in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to load the entire Flash page buffer before executing Page Write. Test-Logic-Reset Run-Test/Idle Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR Select-IR Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR Select-DR Scan Capture-DR 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 |
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