ATmega1284P datasheet(131/380 Pages) ATMEL

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131

8059D–AVR–11/09

ATmega1284P

Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O/8)

14.11 Register Description

14.11.1

TCCRnA – Timer/Counter n Control Register A

• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A

• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B

The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respec-

tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output

overrides the normal port functionality of the I/O pin it is connected to. If one or both of the

COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-

ing to the OCnA or OCnB pin must be set in order to enable the output driver.

When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen-

dent of the WGMn3:0 bits setting. Table 14-2 on page 131 shows the COMnx1:0 bit functionality

when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).

TOVn(FPWM)

and ICF n(if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1

TOP

TOP - 1

TOP - 2

Old OCRnx Value

New OCRnx Value

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

3210

COMnA1

COMnA0

COMnB1

COMnB0

–

WGMn1

WGMn0

TCCRnA

Read/Write

R/W

Initial Value

0000

Table 14-2.

Compare Output Mode, non-PWM

COMnA1/COMnB1

COMnA0/COMnB0

Description

Normal port operation, OCnA/OCnB disconnected.

Toggle OCnA/OCnB on Compare Match.

Clear OCnA/OCnB on Compare Match (Set output to

low level).

Set OCnA/OCnB on Compare Match (Set output to

high level).

ATmega1284P Datasheet(PDF) 131 Page - ATMEL Corporation

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