MPC8548CVTAQJB datasheet(126/144 Pages) FREESCALE

126 / 144 page

MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

126

Freescale Semiconductor

Clocking

19.3

e500 Core PLL Ratio

Table 78 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This

ratio is determined by the binary value of LBCTL, LALE, and LGPL2 at power up, as shown in Table 78.

19.4

Frequency Options

Table 79 shows the expected frequency values for the platform frequency when using a CCB clock to

SYSCLK ratio in comparison to the memory bus clock speed.

Table 78. e500 Core to CCB Clock Ratio

Binary Value of

LBCTL, LALE, LGPL2

Signals

e500 core:CCB Clock Ratio

Binary Value of

LBCTL, LALE, LGPL2

Signals

e500 core:CCB Clock Ratio

000

4:1

100

2:1

001

9:2

101

5:2

010

Reserved

110

3:1

011

3:2

111

7:2

Table 79. Frequency Options of SYSCLK with Respect to Memory Bus Speeds

CCB to

SYSCLK Ratio

SYSCLK (MHz)

16.66

33.33

41.66

66.66

100

111

133.33

Platform/CCB Frequency (MHz)

333

400

333

400

445

533

333

415

500

400

500

333

533

375

333

417

400

500

400

533

333

500

Note: Due to errata Gen 13 the max sys clk frequency should not exceed 100 MHz if the core clk frequency is below

1200 MHz.

MPC8548CVTAQJB Datasheet(PDF) 126 Page - Freescale Semiconductor, Inc

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