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PIC16F707T-E/ML Datasheet(PDF) 113 Page - Microchip Technology |
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PIC16F707T-E/ML Datasheet(HTML) 113 Page - Microchip Technology |
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113 / 284 page  2010 Microchip Technology Inc. Preliminary DS41418A-page 113 PIC16F707/PIC16LF707 REGISTER 14-1: TxCON: TIMERA/TIMERB CONTROL REGISTER R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMRxON — TMRxCS TMRxSE TMRxPSA TMRxPS2 TMRxPS1 TMRxPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMRxON: TimerA/TimerB On/Off Control bit 1 = Timerx is enabled 0 = Timerx is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 TMRxCS: TMRx Clock Source Select bit 1 = Transition on TxCKI pin or CPSxOSC signal 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMRxSE: TMRx Source Edge Select bit 1 = Increment on high-to-low transition on TxCKI pin 0 = Increment on low-to-high transition on TxCKI pin bit 3 TMRxPSA: Prescaler Assignment bit 1 = Prescaler is disabled. Timer clock input bypasses prescaler. 0 = Prescaler is enabled. Timer clock input comes from the prescaler output. bit 2-0 TMRxPS<2:0>: Prescaler Rate Select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 BIT VALUE TMRx RATE TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH TIMERA/B Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CPSACON0 CPSAON CPSARM — — CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000 CPSBCON0 CPSBON CPSBRM — — CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000 PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE 0000 ---0 0000 ---0 PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF 0000 ---0 0000 ---0 TACON TMRAON — TACS TASE TAPSA TAPS2 TAPS1 TAPS0 0-00 0000 0-00 0000 TBCON TMRBON — TBCS TBSE TBPSA TBPS2 TBPS1 TBPS0 0-00 0000 0-00 0000 TMRA TimerA Module Register 0000 0000 0000 0000 TMRB TimerB Module Register 0000 0000 0000 0000 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 Legend: – = Unimplemented locations, read as ‘0’. Shaded cells are not used by the TimerA/B modules. |
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