 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PIC16F1824-E/ML Datasheet(PDF) 252 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC16F1824-E/ML Datasheet(HTML) 252 Page - Microchip Technology |
|
|
252 / 420 page  PIC16F/LF1824/1828 DS41419A-page 252 Preliminary 2010 Microchip Technology Inc. 24.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP1 clock is much faster than the system clock. In Slave mode, when MSSP1 interrupts are enabled, after the master completes sending data, an MSSP1 interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP1 inter- rupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmis- sion/reception will remain in that state until the device wakes. After the device returns to Run mode, the mod- ule will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP1 interrupt flag bit will be set and if enabled, will wake the device. TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — —ANSA4 — ANSA2 ANSA1 ANSA0 127 ANSELB(1) ANSB7 ANSB6 ANSB5 ANSB4 — — — —133 ANSELC ANSC7(1) ANSC6(1) — — ANSC3 ANSC2 ANSC1 ANSC0 133 APFCON0 RXDTSEL SDOSEL(2) SSSEL(2) — T1GSEL TXCKSEL — — 122 INLVLA(3) — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128 INLVLA(4) — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128 INLVLB(1) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — —133 INLVLC(3) INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139 INLVLC(4) INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 245* SSP1CON1 WCOL SSP1OV SSPEN CKP SSPM<3:0> 291 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 293 SSP1STAT SMP CKE D/A P S R/W UA BF 290 TRISA(3) — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126 TRISA(4) — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126 TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — —132 TRISC(3) TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 TRISC(4) TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode. * Page provides register information. Note 1: PIC16F/LF1828 only. 2: PIC16F/LF1824 only. 3: Unshaded cells apply to PIC16F/LF1828 only. 4: Unshaded cells apply to PIC16F/LF1824 only. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
