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PIC16F1824-E/ML Datasheet(PDF) 414 Page - Microchip Technology |
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PIC16F1824-E/ML Datasheet(HTML) 414 Page - Microchip Technology |
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414 / 420 page  PIC16F/LF1824/1828 DS41419A-page 414 Preliminary 2010 Microchip Technology Inc. SSPxOV ............................................................................ 279 SSPxOV Status Flag......................................................... 279 SSPxSTAT Register.......................................................... 290 R/W Bit ...................................................................... 258 Stack ................................................................................... 45 Accessing.................................................................... 45 Reset........................................................................... 47 Stack Overflow/Underflow................................................... 82 STATUS Register................................................................ 26 SUBWFB........................................................................... 349 T T1CON Register.......................................................... 33, 195 T1GCON Register............................................................. 196 T2CON Register.................................................................. 33 T4CON Register.................................................................. 41 T6CON Register.................................................................. 41 Thermal Considerations .................................................... 364 Timer0 ............................................................................... 183 Associated Registers ................................................ 185 Operation .................................................................. 183 Specifications............................................................ 372 Timer1 ............................................................................... 187 Associated registers.................................................. 197 Asynchronous Counter Mode ................................... 189 Reading and Writing ......................................... 189 Clock Source Selection............................................. 188 Interrupt..................................................................... 191 Operation .................................................................. 188 Operation During Sleep ............................................ 191 Oscillator ................................................................... 189 Prescaler................................................................... 189 Specifications............................................................ 372 Timer1 Gate Selecting Source............................................... 189 TMR1H Register ....................................................... 187 TMR1L Register........................................................ 187 Timer2 Associated registers.................................................. 202 Timer2/4/6 ......................................................................... 199 Associated registers.................................................. 202 Timers Timer1 T1CON.............................................................. 195 T1GCON ........................................................... 196 Timer2/4/6 TXCON ............................................................. 201 Timing Diagrams A/D Conversion......................................................... 374 A/D Conversion (Sleep Mode) .................................. 374 Acknowledge Sequence ........................................... 281 Asynchronous Reception .......................................... 302 Asynchronous Transmission..................................... 298 Asynchronous Transmission (Back to Back) ............ 298 Auto Wake-up Bit (WUE) During Normal Operation . 314 Auto Wake-up Bit (WUE) During Sleep .................... 314 Automatic Baud Rate Calibration .............................. 312 Baud Rate Generator with Clock Arbitration ............. 274 BRG Reset Due to SDA Arbitration During Start Condition........................................................... 285 Brown-out Reset (BOR) ............................................ 370 Brown-out Reset Situations ........................................ 81 Bus Collision During a Repeated Start Condition (Case 1) ............................................................ 286 Bus Collision During a Repeated Start Condition (Case 2) ............................................................ 286 Bus Collision During a Start Condition (SCL = 0) ..... 285 Bus Collision During a Stop Condition (Case 1) ....... 287 Bus Collision During a Stop Condition (Case 2) ....... 287 Bus Collision During Start Condition (SDA only) ...... 284 Bus Collision for Transmit and Acknowledge ........... 283 CLKOUT and I/O ...................................................... 368 Clock Synchronization .............................................. 271 Clock Timing............................................................. 366 Comparator Output ................................................... 173 Enhanced Capture/Compare/PWM (ECCP)............. 372 Fail-Safe Clock Monitor (FSCM)................................. 70 First Start Bit Timing ................................................. 275 Full-Bridge PWM Output........................................... 227 Half-Bridge PWM Output .................................. 225, 232 I2C Bus Data............................................................. 380 I2C Bus Start/Stop Bits ............................................. 379 I2C Master Mode (7 or 10-Bit Transmission) ............ 278 I2C Master Mode (7-Bit Reception)........................... 280 I2C Stop Condition Receive or Transmit Mode......... 282 INT Pin Interrupt ......................................................... 91 Internal Oscillator Switch Timing ................................ 65 PWM Auto-shutdown................................................ 231 Firmware Restart .............................................. 230 PWM Direction Change ............................................ 228 PWM Direction Change at Near 100% Duty Cycle... 229 PWM Output (Active-High) ....................................... 223 PWM Output (Active-Low) ........................................ 224 Repeat Start Condition ............................................. 276 Reset Start-up Sequence ........................................... 83 Reset, WDT, OST and Power-up Timer ................... 369 Send Break Character Sequence............................. 315 SPI Master Mode (CKE = 1, SMP = 1) ..................... 377 SPI Mode (Master Mode).......................................... 248 SPI Slave Mode (CKE = 0) ....................................... 378 SPI Slave Mode (CKE = 1) ....................................... 378 Synchronous Reception (Master Mode, SREN) ....... 319 Synchronous Transmission ...................................... 317 Synchronous Transmission (Through TXEN) ........... 317 Timer0 and Timer1 External Clock ........................... 371 Timer1 Incrementing Edge ....................................... 191 Two Speed Start-up.................................................... 68 USART Synchronous Receive (Master/Slave) ......... 376 USART Synchronous Transmission (Master/Slave) .................................................. 376 Wake-up from Interrupt............................................. 102 Timing Diagrams and Specifications PLL Clock ................................................................. 367 Timing Parameter Symbology .......................................... 365 Timing Requirements I2C Bus Data............................................................. 381 SPI Mode .................................................................. 379 TINLVLC Register............................................................. 139 TMR0 Register.................................................................... 33 TMR1H Register ................................................................. 33 TMR1L Register.................................................................. 33 TMR2 Register.................................................................... 33 TMR4 Register.................................................................... 41 TMR6 Register.................................................................... 41 TRIS.................................................................................. 350 TRISA Register........................................................... 34, 126 TRISB ............................................................................... 130 TRISB Register........................................................... 34, 132 TRISC ............................................................................... 135 TRISC Register........................................................... 34, 137 Two-Speed Clock Start-up Mode........................................ 67 |
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