PIC16F1824-ESLASHML datasheet(163/420 Pages) MICROCHIP

163 / 420 page

 2010 Microchip Technology Inc.

Preliminary

DS41419A-page 163

PIC16F/LF1824/1828

16.4

Low Power Voltage State

In order for the DAC module to consume the least

amount of power, one of the two voltage reference input

sources to the resistor ladder must be disconnected.

Either the positive voltage source, (VSRC+), or the

negative voltage source, (VSRC-) can be disabled.

The negative voltage source is disabled by setting the

DACLPS bit in the DACCON0 register. Clearing the

DACLPS bit in the DACCON0 register disables the

positive voltage source.

16.4.1

OUTPUT CLAMPED TO POSITIVE

VOLTAGE SOURCE

The DAC output voltage can be set to VSRC+ with the

least amount of power consumption by performing the

following:

• Clearing the DACEN bit in the DACCON0 register.

• Setting the DACLPS bit in the DACCON0 register.

• Configuring the DACPSS bits to the proper

positive source.

• Configuring the DACR<4:0> bits to ‘11111’ in the

DACCON1 register.

This is also the method used to output the voltage level

from the FVR to an output pin. See Section FIGURE

16-2: “Voltage Reference Output Buffer Example”

for more information.

Reference Figure 16-3 for output clamping examples.

16.4.2

OUTPUT CLAMPED TO NEGATIVE

VOLTAGE SOURCE

The DAC output voltage can be set to VSRC- with the

least amount of power consumption by performing the

following:

• Clearing the DACEN bit in the DACCON0 register.

• Clearing the DACLPS bit in the DACCON0 register.

• Configuring the DACNSS bits to the proper

negative source.

• Configuring the DACR<4:0> bits to ‘00000’ in the

DACCON1 register.

This allows the comparator to detect a zero-crossing

while not consuming additional current through the DAC

module.

Reference Figure 16-3 for output clamping examples.

FIGURE 16-3:

OUTPUT VOLTAGE CLAMPING EXAMPLES

16.5

Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the DACCON0 register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

16.6

Effects of a Reset

A device Reset affects the following:

• DAC is disabled.

• DAC output voltage is removed from the

DACOUT pin.

• The DACR<4:0> range select bits are cleared.

DAC Voltage Ladder

(see Figure 16-1)

VSRC+

DACEN = 0

DACLPS = 1

DACR<4:0> = 11111

VSRC-

DAC Voltage Ladder

(see Figure 16-1)

VSRC+

DACEN = 0

DACLPS = 0

DACR<4:0> = 00000

VSRC-

Output Clamped to Positive Voltage Source

Output Clamped to Negative Voltage Source

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