PIC18F23K20 datasheet(161/456 Pages) MICROCHIP

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DS41303G-page 161

PIC18F2XK20/4XK20

13.2

Clock Source Selection

The TMR1CS bit of the T1CON register is used to

select the clock source. When TMR1CS = 0, the clock

source is FOSC/4. When TMR1CS = 1, the clock source

is supplied externally.

13.2.1

INTERNAL CLOCK SOURCE

When the internal clock source is selected, the

TMR1H:TMR1L register pair will increment on multiples

of TCY as determined by the Timer1 prescaler.

13.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

When counting, Timer1 is incremented on the rising

edge of the external clock input T1CKI. In addition, the

Counter mode clock can be synchronized to the

microcontroller system clock or run asynchronously.

If an external clock oscillator is needed (and the

microcontroller is using the INTOSC without CLKOUT),

Timer1 can use the LP oscillator as a clock source.

13.2.3

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TTMR1L register

pair.

13.3

Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

13.4

Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

continues to increment asynchronous to the internal

phase clocks. The timer will continue to run during

Sleep and can generate an interrupt on overflow,

which will wake-up the processor. However, special

precautions in software are needed to read/write the

timer (see Section 13.2.3 “Reading and Writing

Timer1 in Asynchronous Counter Mode”).

FIGURE 13-3:

TIMER1 INCREMENTING EDGE

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after one or more

of the following conditions (see Figure 13-3):

• Timer1 is enabled after POR or BOR

Reset

• A write to TMR1H or TMR1L

• Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON = 1) when T1CKI

is low.

Note 1: When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1:

Arrows indicate counter increments.

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of

the clock.

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