PIC18F23K20-ESLASHML datasheet(208/456 Pages) MICROCHIP

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PIC18F2XK20/4XK20

DS41303G-page 208

 2010 Microchip Technology Inc.

17.4.3.2

Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register and the SDA line is held low

(ACK).

When the address byte overflow condition exists, then

the no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF bit of the SSPSTAT

An MSSP interrupt is generated for each data transfer

byte. Flag bit, SSPIF of the PIR1 register, must be

cleared by software. The SSPSTAT register is used to

determine the status of the byte.

When the SEN bit of the SSPCON2 register is set,

SCK/SCL will be held low (clock stretch) following

each data transfer. The clock must be released by

setting the CKP bit of the SSPCON1 register. See

Section 17.4.4 “Clock Stretching” for more detail.

17.4.3.3

Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin SCK/SCL is held low

regardless

of SEN (see

Section 17.4.4

“Clock

Stretching” for more detail). By stretching the clock,

the master will be unable to assert another clock pulse

until the slave is done preparing the transmit data. The

transmit data must be loaded into the SSPBUF register

which also loads the SSPSR register. Then pin

SCK/SCL should be enabled by setting the CKP bit of

the SSPCON1 register. The eight data bits are shifted

out on the falling edge of the SCL input. This ensures

that the SDA signal is valid during the SCL high time

(Figure 17-9).

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. If the SDA

line is high (not ACK), then the data transfer is

complete. In this case, when the ACK is latched by the

slave, the slave logic is reset (resets SSPSTAT

of the Start bit. If the SDA line was low (ACK), the next

transmit data must be loaded into the SSPBUF register.

Again, pin SCK/SCL must be enabled by setting bit

CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared by software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

PIC18F23K20-E/ML Datasheet(PDF) 208 Page - Microchip Technology

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