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PIC18F23K20-E/ML Datasheet(PDF) 237 Page - Microchip Technology

Part # PIC18F23K20-E/ML
Description  28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
PDF  456 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F23K20-E/ML Datasheet(HTML) 237 Page - Microchip Technology

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 2010 Microchip Technology Inc.
DS41303G-page 237
PIC18F2XK20/4XK20
18.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent
of
device
program
execution.
The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system.
Full-Duplex
mode
is
useful
for
communications with peripheral systems, such as CRT
terminals
and
personal
computers.
Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock and data polarity
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 18-1 and Figure 18-2.
FIGURE 18-1:
EUSART TRANSMIT BLOCK DIAGRAM
TXIF
TXIE
Interrupt
TXEN
TX9D
MSb
LSb
Data Bus
TXREG Register
Transmit Shift Register (TSR)
(8)
0
TX9
TRMT
TX/CK pin
Pin Buffer
and Control
8
SPBRG
SPBRGH
BRG16
FOSC
÷ n
n
+ 1
Multiplier
x4
x16 x64
SYNC
1X00
0
BRGH
X110
0
BRG16
X101
0
Baud Rate Generator
•• •



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