PIC18F23K20-ESLASHML datasheet(244/456 Pages) MICROCHIP

244 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 244

 2010 Microchip Technology Inc.

18.1.2.9

Asynchronous Reception Set-up:

Initialize the SPBRGH:SPBRG register pair and

the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 18.3 “EUSART

Baud Rate Generator (BRG)”).

Set the RX/DT and TX/CK TRIS controls to ‘1’.

Enable the serial port by setting the SPEN bit

and the RX/DT pin TRIS bit. The SYNC bit must

be clear for asynchronous operation.

If interrupts are desired, set the RCIE interrupt

enable bit and set the GIE and PEIE bits of the

INTCON register.

If 9-bit reception is desired, set the RX9 bit.

Set the DTRXP if inverted receive polarity is

desired.

Enable reception by setting the CREN bit.

The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

10. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

18.1.2.10

9-bit Address Detection Mode Set-up

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

Initialize the SPBRGH, SPBRG register pair and

the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 18.3 “EUSART

Baud Rate Generator (BRG)”).

Set the RX/DT and TX/CK TRIS controls to ‘1’.

Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

If interrupts are desired, set the RCIE interrupt

enable bit and set the GIE and PEIE bits of the

INTCON register.

Enable 9-bit reception by setting the RX9 bit.

Enable address detection by setting the ADDEN

bit.

Set the DTRXP if inverted receive polarity is

desired.

Enable reception by setting the CREN bit.

The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCIE interrupt enable bit

was also set.

10. Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

11. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

device’s address.

12. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

13. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

PIC18F23K20-E/ML Datasheet(PDF) 244 Page - Microchip Technology

PIC18F23K20-E/ML Datasheet(HTML) 244 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL