PIC18F23K20-ESLASHML datasheet(257/456 Pages) MICROCHIP

257 / 456 page

 2010 Microchip Technology Inc.

DS41303G-page 257

PIC18F2XK20/4XK20

18.4

EUSART Synchronous Mode

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary

circuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

There are two signal lines in Synchronous mode: a

bidirectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and

transmit shift registers. Since the data line is

bidirectional, synchronous operation is half-duplex

only. Half-duplex refers to the fact that master and

slave devices can receive and transmit data but not

both simultaneously. The EUSART can operate as

either a master or slave device.

Start and Stop bits are not used in synchronous

transmissions.

18.4.1

SYNCHRONOUS MASTER MODE

The following bits are used to configure the EUSART

for Synchronous Master operation:

• SYNC = 1

• CSRC = 1

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCSTA

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART. If the RX/DT or TX/CK pins are shared with an

analog peripheral the analog I/O functions must be

disabled by clearing the corresponding ANSEL bits.

The TRIS bits corresponding to the RX/DT and TX/CK

pins should be set.

18.4.1.1

Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a master transmits the clock on the TX/CK line. The

TX/CK pin output driver is automatically enabled when

the EUSART is configured for synchronous transmit or

receive operation. Serial data bits change on the leading

edge to ensure they are valid at the trailing edge of each

clock. One clock cycle is generated for each data bit.

Only as many clock cycles are generated as there are

data bits.

18.4.1.2

Clock Polarity

A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the CKTXP

bit of the BAUDCON register. Setting the CKTXP bit

sets the clock Idle state as high. When the CKTXP bit

is set, the data changes on the falling edge of each

clock and is sampled on the rising edge of each clock.

Clearing the CKTXP bit sets the Idle state as low. When

the CKTXP bit is cleared, the data changes on the

rising edge of each clock and is sampled on the falling

edge of each clock.

18.4.1.3

Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are automat-

ically enabled when the EUSART is configured for

synchronous master transmit operation.

A transmission is initiated by writing a character to the

TXREG register. If the TSR still contains all or part of a

previous character the new character data is held in the

TXREG until the last bit of the previous character has

been transmitted. If this is the first character, or the pre-

vious character has been completely flushed from the

TSR, the data in the TXREG is immediately transferred

to the TSR. The transmission of the character com-

mences immediately following the transfer of the data

to the TSR from the TXREG.

Each data bit changes on the leading edge of the mas-

ter clock and remains valid until the subsequent leading

clock edge.

18.4.1.4

Data Polarity

The polarity of the transmit and receive data can be

controlled with the DTRXP bit of the BAUDCON regis-

ter. The default state of this bit is ‘0’ which selects high

true transmit and receive data. Setting the DTRXP bit

to ‘1’ will invert the data resulting in low true transmit

and receive data.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

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