PIC18F23K20-ESLASHML datasheet(308/456 Pages) MICROCHIP

308 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 308

 2010 Microchip Technology Inc.

23.2

Watchdog Timer (WDT)

For PIC18F2XK20/4XK20 devices, the WDT is driven

by the LFINTOSC source. When the WDT is enabled,

the clock source is also enabled. The nominal WDT

period is 4 ms and has the same stability as the LFIN-

TOSC oscillator.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is

selected by a multiplexer, controlled by bits in Configu-

ration Register 2H. Available periods range from 4 ms

to 131.072 seconds (2.18 minutes). The WDT and

postscaler are cleared when any of the following events

occur: a SLEEP or CLRWDT instruction is executed, the

IRCF bits of the OSCCON register are changed or a

clock failure has occurred.

FIGURE 23-1:

WDT BLOCK DIAGRAM

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

2: Changing the setting of the IRCF bits of

the OSCCON register clears the WDT

and postscaler counts.

3: When a CLRWDT instruction is executed,

the postscaler count will be cleared.

LFINTOSC Source

WDT

Wake-up

Reset

WDT Counter

Programmable Postscaler

1:1 to 1:32,768

Enable WDT

WDTPS<3:0>

SWDTEN

WDTEN

CLRWDT

from Power

Reset

All Device Resets

Sleep

128

Change on IRCF bits

Managed Modes

PIC18F23K20-E/ML Datasheet(PDF) 308 Page - Microchip Technology

PIC18F23K20-E/ML Datasheet(HTML) 308 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL