PIC18F23K20-ESLASHML datasheet(388/456 Pages) MICROCHIP

388 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 388

 2010 Microchip Technology Inc.

FIGURE 26-7:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

FIGURE 26-8:

BROWN-OUT RESET TIMING

TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

TmcL

MCLR Pulse Width (low)

—

s

TWDT

Watchdog Timer Time-out Period

(no postscaler)

3.5

4.1

4.7

1:1 prescaler

TOST

Oscillation Start-up Timer Period

1024 TOSC

—

1024 TOSC

—TOSC = OSC1 period

TPWRT

Power-up Timer Period

54.8

64.4

74.1

TIOZ

I/O High-Impedance from MCLR

Low or Watchdog Timer Reset

—2

—

s

TBOR

Brown-out Reset Pulse Width

200

—

sVDD  BVDD (see D005)

TIVRST

Internal Reference Voltage Stable

—

s

THLVD

High/Low-Voltage Detect Pulse Width

200

—

sVDD  VHLVD

TCSD

CPU Start-up Time

—

s

TIOBST

Time for HF-INTOSC to Stabilize

—

0.25

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

I/O pins

Note:

Refer to Figure 26-4 for load conditions.

VDD

BVDD

VBGAP = 1.2V

VIVRST

Enable Internal

Internal Reference

Reference Voltage

Voltage Stable

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