PIC18F23K20-ESLASHML datasheet(163/456 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41303G-page 163

PIC18F2XK20/4XK20

13.6.2

LOW-POWER TIMER1 OPTION

The Timer1 oscillator can operate at two distinct levels

of power consumption based on device configuration.

When

the

LPT1OSC

Configuration

bit

the

CONFIG3H register is set, the Timer1 oscillator oper-

ates in a low-power mode. When LPT1OSC is not set,

Timer1 operates at a higher power level. Power con-

sumption for a particular mode is relatively constant,

regardless of the device’s operating mode. The default

Timer1 configuration is the higher power mode.

As the low-power Timer1 mode tends to be more

sensitive to interference, high noise environments may

cause some oscillator instability. The low-power option is,

therefore, best suited for low noise applications where

power conservation is an important design consideration.

13.6.3

TIMER1 OSCILLATOR LAYOUT

CONSIDERATIONS

The Timer1 oscillator circuit draws very little power

during operation. Due to the low-power nature of the

oscillator, it may also be sensitive to rapidly changing

signals in close proximity.

The oscillator circuit, shown in Figure 13-4, should be

located as close as possible to the microcontroller.

There should be no circuits passing within the oscillator

circuit boundaries other than VSS or VDD.

If a high-speed circuit must be located near the oscilla-

tor (such as the CCP1 pin in Output Compare or PWM

mode, or the primary oscillator using the OSC2 pin), a

grounded guard ring around the oscillator circuit, as

shown in Figure 13-5, may be helpful when used on a

single-sided PCB or in addition to a ground plane.

FIGURE 13-5:

OSCILLATOR CIRCUIT

WITH GROUNDED

GUARD RING

13.7

Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

Timer1 interrupt, if enabled, is generated on overflow,

which is latched in the TMR1IF interrupt flag bit of the

PIR1 register. This interrupt can be enabled or disabled

by setting or clearing the TMR1IE Interrupt Enable bit

of the PIE1 register.

13.8

Resetting Timer1 Using the CCP

Special Event Trigger

If either of the CCP modules is configured to use Timer1

and generate a Special Event Trigger in Compare mode

(CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will

reset Timer1. The trigger from CCP2 will also start an

A/D conversion if the A/D module is enabled (see

Section 11.3.4 “Special Event Trigger” for more

information).

The module must be configured as either a timer or a

synchronous counter to take advantage of this feature.

When used this way, the CCPRH:CCPRL register pair

effectively becomes a period register for Timer1.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

special Event Trigger, the write operation will take

precedence.

VDD

OSC1

VSS

OSC2

RC0

RC1

RC2

Note: Not drawn to scale.

Note:

The Special Event Triggers from the CCP2

module will not set the TMR1IF interrupt

flag bit of the PIR1 register.

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