PIC18F23K20-ESLASHML datasheet(175/456 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41303G-page 175

PIC18F2XK20/4XK20

16.4

PWM (Enhanced Mode)

The Enhanced PWM Mode can generate a PWM signal

on up to four different output pins with up to 10-bits of

resolution. It can do this through four different PWM

output modes:

• Single PWM

• Half-Bridge PWM

• Full-Bridge PWM, Forward mode

• Full-Bridge PWM, Reverse mode

To select an Enhanced PWM mode, the P1M bits of the

CCP1CON register must be set appropriately.

The PWM outputs are multiplexed with I/O pins and are

designated P1A, P1B, P1C and P1D. The polarity of the

PWM pins is configurable and is selected by setting the

CCP1M bits in the CCP1CON register appropriately.

Table 16-1 shows the pin assignments for each

Enhanced PWM mode.

Figure 16-1 shows an example of a simplified block

diagram of the Enhanced PWM module.

FIGURE 16-1:

EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

TABLE 16-1:

EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES

Note:

The PWM Enhanced mode is available on

the

Enhanced

Capture/Compare/PWM

module (CCP1) only.

Note:

prevent

the

generation

incomplete waveform when the PWM is

first enabled, the ECCP module waits until

the start of a new PWM period before

generating a PWM signal.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(1)

Duty Cycle Registers

DC1B<1:0>

Clear Timer2,

toggle PWM pin and

latch duty cycle

Note

The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit

time base.

TRIS

CCP1/P1A

TRIS

P1B

TRIS

P1C

TRIS

P1D

Output

Controller

P1M<1:0>

CCP1M<3:0>

PWM1CON

CCP1/P1A

P1B

P1C

P1D

Note 1: The TRIS register value for each PWM output must be configured appropriately.

2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins.

3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.

ECCP Mode

P1M<1:0>

CCP1/P1A

P1B

P1C

P1D

Single

Yes(1)

Half-Bridge

Yes

Full-Bridge, Forward

Yes

Full-Bridge, Reverse

Yes

Note 1:

Outputs are enabled by pulse steering in Single mode. See Register 16-4.

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