PIC24F16KA102 datasheet(166/254 Pages) MICROCHIP

166 / 254 page

PIC24F16KA102 FAMILY

DS39927B-page 164

Preliminary

FIGURE 20-2:

CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1

20.1

User Interface

20.1.1

DATA INTERFACE

To start serial shifting, a value of ‘1’ must be written to

the CRCGO bit.

The module incorporates a FIFO that is 8-level deep

when PLEN<3:0> > 7, and 16 deep, otherwise. The

data for which the CRC is to be calculated must first be

written into the FIFO. The smallest data element that

can be written into the FIFO is one byte.

For example, if PLEN = 5, then the size of the data is

PLEN + 1 = 6. The data must be written as follows:

data<5:0> = crc_input<5:0>

data<7:6> = bxx

Once data is written into the CRCWDAT MSb (as

defined by PLEN), the value of the VWORD bits

(CRCCON<12:8>) increments by one. The serial

shifter starts shifting data into the CRC engine when

CRCGO = 1 and VWORD<4:0> > 0. When the Most

Significant bit (MSb) is shifted out, the VWORD bits

decrement by one. The serial shifter continues shifting

until the VWORD bits reach zero. Therefore, for a given

value of PLEN, it will take (PLEN + 1) * VWORD

number of clock cycles to complete the CRC

calculations.

When the VWORD bits reach 8 (or 16), the CRCFUL bit

will be set. When the VWORD bits reach 0, the

CRCMPT bit will be set.

To continually feed data into the CRC engine, the

recommended mode of operation is to initially “prime”

the FIFO with a sufficient number of words so no

interrupt is generated before the next word can be

written. Once that is done, start the CRC by setting the

CRCGO bit to ‘1’. From that point onward, the VWORD

bits should be polled. If they read less than 8 or 16,

another word can be written into the FIFO.

To empty words already written into a FIFO, the

CRCGO bit must be set to ‘1’ and the CRC shifter

allowed to run until the CRCMPT bit is set.

Also, to get the correct CRC reading, it will be

necessary to wait for the CRCMPT bit to go high before

reading the CRCWDAT register.

If a word is written when the CRCFUL bit is set, the

VWORD Pointer will roll over to 0. The hardware will

then behave as if the FIFO is empty. However, the

condition to generate an interrupt will not be met;

therefore, no interrupt will be generated (see

Section 20.1.2 “Interrupt Operation”

At least one instruction cycle must pass after a write to

CRCWDAT before a read of the VWORD bits is done.

20.1.2

INTERRUPT OPERATION

When the VWORD<4:0> bits make a transition from a

value of ‘1’ to ‘0’, an interrupt will be generated.

20.2

Operation in Power Save Modes

20.2.1

SLEEP MODE

If Sleep mode is entered while the module is operating,

the module will be suspended in its current state until

clock execution resumes.

20.2.2

IDLE MODE

To continue full module operation in Idle mode, the

CSIDL bit must be cleared prior to entry into the mode.

If CSIDL = 1, the module will behave the same way as

it does in Sleep mode; pending interrupt events will be

passed on, even though the module clocks are not

available.

BIT 0

clk

BIT 4

clk

BIT 5

clk

BIT 12

clk

XOR

SDOx

CRC Read Bus

CRC Write Bus

BIT 15

clk

PIC24F16KA102 Datasheet(PDF) 166 Page - Microchip Technology

PIC24F16KA102 Datasheet(HTML) 166 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL