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I.MX27 Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc |
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I.MX27 Datasheet(HTML) 49 Page - Freescale Semiconductor, Inc |
49 / 148 page ![]() i.MX27 and i.MX27L Data Sheet, Rev. 1.5 Freescale Semiconductor 49 Electrical Characteristics Figure 8. ATA interface Signals Timing Diagram 4.2.4 Digital Audio Mux (AUDMUX) The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSI, SAP) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by SSI and SAP modules. Please refer to their respective electrical specifications. 4.2.5 CMOS Sensor Interface (CSI) This section describes the electrical information (AC timing) of the CSI. 4.2.5.1 Gated Clock Mode Timing VSYNC, HSYNC, and PIXCLK signals are used in this mode. A frame starts with a rising/falling edge on VSYNC, then HSYNC goes high and holds for the entire line. The pixel clock is valid as long as HSYNC is high. Figure 9 and Figure 10 depict the gated clock mode timings of CSI, and Table 21 lists the timing parameters. ATA Interface Signals SI1 SI2 |
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