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I.MX27 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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I.MX27 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 148 page  i.MX27 and i.MX27L Data Sheet, Rev. 1.5 10 Freescale Semiconductor Functional Description and Application Information 2.3.2 AHB-Lite IP Interface Module (AIPI) The AIPI acts as an interface between the ARM Advanced High-performance Bus Lite. (AHB-Lite) and lower bandwidth peripherals conforming to the IP bus specification Rev 2.0. There are two AIPI modules in i.MX27/MX27L processors. The following list summarizes the key features of the AIPI: • All peripheral read transactions require a minimum of two system clocks (R-AHB side) and all write transactions require a minimum of three system clocks (R-AHB side). • The AIPI supports 8-bit, 16-bit, and 32-bit IP bus peripherals. Byte, half word, and full word reads and writes are supported. • The AIPI supports multi-cycle accesses by providing 16-bit to 8-bit peripherals operations and 32-bit to both 16-bit and 8-bit peripherals operations. • The AIPI supports 31 external IP bus peripherals each with a 4-Kbyte memory map (a slot). 2.3.3 ARM926EJ-S Interrupt Controller (AITC) The ARM926EJ-S Interrupt Controller (AITC) is a 32-bit peripheral that collects interrupt requests from up to 64 sources and provides an interface to the ARM926EJ-S core. The AITC includes software controlled priority levels for normal interrupts. The AITC performs the following functions: • Supports up to 64 interrupt sources • Supports fast and normal interrupts • Selects normal or fast interrupt request for any interrupt source • Indicates pending interrupt sources via a register for normal and fast interrupts • Indicates highest priority interrupt number via register. (Can be used as a table index.) • Independently can enable or disable any interrupt source • Provides a mechanism for software to schedule an interrupt • Supports up to 16 software controlled priority levels for normal interrupts and priority masking • Can single-bit disable all normal interrupts and all fast interrupts. (Used in enabling of secure operations.) 2.3.4 ARM926EJ-S Platform The ARM926EJ-S (ARM926) is a member of the ARM9 family of general-purpose microprocessors targeted at multi-tasking applications. The ARM926 supports the 32-bit ARM and 16-bit Thumb instructions sets. The ARM926 includes features for efficient execution of Java byte codes. A JTAG port is provided to support the ARM Debug Architecture, along with associated signals to support the ETM9 real-time trace module. The ARM926EJ-S is a Harvard cached architecture including an ARM9EJ-S integer core, a Memory Management Unit (MMU), separate instruction and data AMBA AHB interfaces, separate instruction and data caches, and separate instruction and data tightly coupled memory (TCM) interfaces. The ARM926 co-processor, instruction TCM, and data TCM interfaces will be tied off within the ARM926 Platform and will not be available for external connection. |
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